C8051F980-C-GM Datasheet, PDF (6/325 Pages) Silicon Laboratories – Ultra Low Power, 8-2 kB Flash, Capacitive Sensing MCU

C8051F99x-C8051F98x
22.3.SMBus Operation ........................................................................................... 237
22.3.1.Transmitter vs. Receiver ........................................................................ 237
22.3.2.Arbitration............................................................................................... 238
22.3.3.Clock Low Extension.............................................................................. 238
22.3.4.SCL Low Timeout................................................................................... 238
22.3.5.SCL High (SMBus Free) Timeout .......................................................... 238
22.4.Using the SMBus............................................................................................ 239
22.4.1.SMBus Configuration Register............................................................... 240
22.4.2.SMB0CN Control Register ..................................................................... 243
22.4.3.Hardware Slave Address Recognition ................................................... 246
22.4.4.Data Register ......................................................................................... 248
22.5.SMBus Transfer Modes.................................................................................. 249
22.5.1.Write Sequence (Master) ....................................................................... 249
22.5.2.Read Sequence (Master) ....................................................................... 250
22.5.3.Write Sequence (Slave) ......................................................................... 251
22.5.4.Read Sequence (Slave) ......................................................................... 252
22.6.SMBus Status Decoding................................................................................. 252
23. UART0.................................................................................................................... 257
23.1.Enhanced Baud Rate Generation................................................................... 258
23.2.Operational Modes ......................................................................................... 259
23.2.1.8-Bit UART ............................................................................................. 259
23.2.2.9-Bit UART ............................................................................................. 260
23.3.Multiprocessor Communications .................................................................... 260
24. Enhanced Serial Peripheral Interface (SPI0)...................................................... 265
24.1.Signal Descriptions......................................................................................... 266
24.1.1.Master Out, Slave In (MOSI).................................................................. 266
24.1.2.Master In, Slave Out (MISO).................................................................. 266
24.1.3.Serial Clock (SCK) ................................................................................. 266
24.1.4.Slave Select (NSS) ................................................................................ 266
24.2.SPI0 Master Mode Operation ......................................................................... 266
24.3.SPI0 Slave Mode Operation ........................................................................... 268
24.4.SPI0 Interrupt Sources ................................................................................... 269
24.5.Serial Clock Phase and Polarity ..................................................................... 269
24.6.SPI Special Function Registers ...................................................................... 271
25. Timers.................................................................................................................... 278
25.1.Timer 0 and Timer 1 ....................................................................................... 280
25.1.1.Mode 0: 13-bit Counter/Timer ................................................................ 280
25.1.2.Mode 1: 16-bit Counter/Timer ................................................................ 281
25.1.3.Mode 2: 8-bit Counter/Timer with Auto-Reload...................................... 282
25.1.4.Mode 3: Two 8-bit Counter/Timers (Timer 0 Only)................................. 283
25.2.Timer 2 .......................................................................................................... 288
25.2.1.16-bit Timer with Auto-Reload................................................................ 288
25.2.2.8-bit Timers with Auto-Reload................................................................ 289
25.2.3.Comparator 0/SmaRTClock Capture Mode ........................................... 290
25.3.Timer 3 .......................................................................................................... 294
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Rev. 1.2