C8051F980-C-GM Datasheet, PDF (147/325 Pages) Silicon Laboratories – Ultra Low Power, 8-2 kB Flash, Capacitive Sensing MCU

C8051F99x-C8051F98x
SFR Definition 13.6. EIP2: Extended Interrupt Priority 2
Bit
7
6
5
4
3
2
1
0
Name
PCSEOS PCSDC PCSCPT
PRTC0F PMAT PWARN
Type
R
R/W
R/W
R/W
R
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
SFR Page = All; SFR Address = 0xF7
Bit Name
Function
7 Unused Read = 0b. Write = Don’t care.
6 PCSEOS Capacitive Sense End of Scan Interrupt Priority Control.
0: Capacitive Sense End of Scan interrupt set to low priority level.
1: Capacitive Sense End of Scan interrupt set to high priority level.
5 PCSDC Capacitive Sense Digital Comparator Interrupt Priority Control.
0: Capacitive Sense Digital Comparator interrupt set to low priority level.
1: Capacitive Sense Digital Comparator interrupt set to high priority level.
4 PCSCPT Capacitive Sense Conversion Complete Interrupt Priority Control.
0: Capacitive Sense Conversion Complete interrupt set to low priority level.
1: Capacitive Sense Conversion Complete interrupt set to high priority level.
3 Unused Read = 0b. Write = Don’t care.
2 PRTC0F SmaRTClock Oscillator Fail Interrupt Priority Control.
This bit sets the priority of the SmaRTClock Alarm interrupt.
0: SmaRTClock Alarm interrupt set to low priority level.
1: SmaRTClock Alarm interrupt set to high priority level.
1
PMAT Port Match Interrupt Priority Control.
This bit sets the priority of the Port Match Event interrupt.
0: Port Match interrupt set to low priority level.
1: Port Match interrupt set to high priority level.
0 PWARN Supply Monitor Early Warning Interrupt Priority Control.
This bit sets the priority of the Supply Monitor Early Warning interrupt.
0: Supply Monitor Early Warning interrupt set to low priority level.
1: Supply Monitor Early Warning interrupt set to high priority level.
Rev. 1.2
147