C8051F980-C-GM Datasheet, PDF (78/325 Pages) Silicon Laboratories – Ultra Low Power, 8-2 kB Flash, Capacitive Sensing MCU

C8051F99x-C8051F98x
SFR Definition 5.5. ADC0TK: ADC0 Burst Mode Track Time
Bit
7
6
5
4
3
2
1
0
Name Reserved
AD0TK[5:0]
Type
R
R
R/W
Reset
0
0
0
1
1
1
1
0
SFR Page = All; SFR Address = 0xBC
Bit Name
Function
7 Reserved Read = 0b; Write = Must Write 0b.
6 Unused Read = 0b; Write = Don’t Care.
5:0 AD0TK[5:0] ADC0 Burst Mode Track Time.
Sets the time delay between consecutive conversions performed in Burst Mode.
The ADC0 Burst Mode Track time is programmed according to the following equa-
tion:
AD0TK = 63 – _^T---5-^t--0^r---^a-_n--^c-_s--^k- – 1_
or
Ttrack = 64 – AD0TK50ns
Notes:
1. If AD0TM is set to 1, an additional 3 SAR clock cycles of Track time will be inserted prior to starting the
conversion.
2. The Burst Mode Track delay is not inserted prior to the first conversion. The required tracking time for the first
conversion should be met by the Burst Mode Power-Up Time.
78
Rev. 1.2