C8051F980-C-GM Datasheet, PDF (59/325 Pages) Silicon Laboratories – Ultra Low Power, 8-2 kB Flash, Capacitive Sensing MCU

C8051F99x-C8051F98x
Table 4.9. SmaRTClock Characteristics
V_DD = 1.8 to 3.6 V; T_A = –40 to +85 °C unless otherwise specified; Using factory-calibrated settings.
Parameter
Conditions
Min
Typ
Max
Oscillator Frequency (LFO)
13.1
16.4
19.7
Units
kHz
Table 4.10. ADC0 Electrical Characteristics
V_DD = 1.8 to 3.6 V, VREF = 1.65 V (REFSL[1:0] = 11), –40 to +85 °C unless otherwise specified.
Parameter
Resolution
Integral Nonlinearity
Differential Nonlinearity
(Guaranteed Monotonic)
Conditions
DC Accuracy
12-bit mode
10-bit mode
12-bit mode¹
10-bit mode
12-bit mode¹
10-bit mode
Min Typ Max Units
12
bits
10
—
±1 ±1.5 LSB
—
±0.5
±1
—
±0.8 ±1
LSB
—
±0.5
±1
Offset Error
12-bit mode
10-bit mode
—
±<1
±2
LSB
—
±<1
±2
Full Scale Error
12-bit mode²
10-bit mode
—
±1
±4
LSB
—
±1 ±2.5
Dynamic performance (10 kHz sine-wave single-ended input, 1 dB below Full Scale, maximum
sampling rate)
Signal-to-Noise Plus Distortion³
12-bit mode
10-bit mode
62
65
—
dB
54
58
—
Signal-to-Distortion³
12-bit mode
10-bit mode
—
76
—
dB
—
73
—
Spurious-Free Dynamic Range³
12-bit mode
10-bit mode
—
82
—
dB
—
75
—
Conversion Rate
SAR Conversion Clock
Normal Power Mode
Low Power Mode
—
— 8.33 MHz
—
—
4.4
Conversion Time in SAR Clocks
10-bit Mode
8-bit Mode
13
11
Track/Hold Acquisition Time
Initial Acquisition
1.5
Subsequent Acquisitions (DC
1.1
input, burst mode)
Throughput Rate
12-bit mode
—
10-bit mode
—
—
— clocks
—
—
—
—
us
—
—
—
75
ksps
—
300
1. INL and DNL specifications for 12-bit mode do not include the first or last four ADC codes.
2. The maximum code in 12-bit mode is 0xFFFC. The Full Scale Error is referenced from the maximum code.
3. Performance in 8-bit mode is similar to 10-bit mode.
Rev. 1.2
59