SI5341_16 Datasheet, PDF (8/53 Pages) Silicon Laboratories – Low-Jitter, 10 or 4-Output, Any-Frequency, Any-Output Clock Generator

Si5341/40 Rev D Data Sheet
Functional Description
3.3.3 Input Selection (IN0, IN1, IN2, XA/XB)
The active clock input is selected using the IN_SEL[1:0] pins or by register control. A register bit determines input selection as pin or
register selectable. There are internal pull ups on the IN_SEL pins.
Table 3.1. Manual Input Selection Using IN_SEL[1:0] Pins
IN_SEL[1:0]
0
0
0
1
1
0
1
1
Selected Input
IN0
IN1
IN2
XA/XB
3.4 Fault Monitoring
The Si5340/41-D provides fault indicators which monitor loss of signal (LOS) of the inputs (IN0, IN1, IN2, XA/XB, FB_IN) and loss of
lock (LOL) for the PLL as shown in the figure below.
IN0
IN0b
IN1
IN1b
IN2
IN2b
÷P₀
LOS0
÷P₁
LOS1
÷P₂
LOS2
XA
XB
FB_IN
FB _INb
OSC
LOSXAB
÷P_fb
LOSFB
Si5341/40
LOL
PD LPF
PLL
÷
Mn
Md
Figure 3.4. LOS and LOL Fault Monitors
3.4.1 Status Indicators
The state of the status monitors are accessible by reading registers through the serial interface or with dedicated pin (LOLb). Each of
the status indicator register bits has a corresponding sticky bit in a separate register location. Once a status bit is asserted its corre-
sponding sticky bit (_FLG) will remain asserted until cleared. Writing a logic zero to a sticky register bit clears its state.
3.4.2 Interrupt Pin (INTRb)
An interrupt pin (INTRb) indicates a change in state with any of the status registers. All status registers are maskable to prevent asser-
tion of the interrupt pin. The state of the INTRb pin is reset by clearing the status registers.
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