SI5341_16 Datasheet, PDF (21/53 Pages) Silicon Laboratories – Low-Jitter, 10 or 4-Output, Any-Frequency, Any-Output Clock Generator

Si5341/40 Rev D Data Sheet
Electrical Specifications
Table 5.3. Input Clock Specifications
(V_DD=1.8V ± 5%, V_DDA=3.3V ± 5%, T_A=-40 to 85°C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
Standard Input Buffer with Differential or Single-Ended - AC-Coupled (IN0/IN0b, IN1/IN1b, IN2/IN2b, FB_IN/FB_INb)
Input Frequency Range
f_IN
Differential
0.008
—
All Single-ended Signals
0.008
—
750
MHz
250
MHz
(including LVCMOS)
Input Voltage Swing¹
V_IN
Differential AC-coupled
100
f_IN < 250 MHz
—
1800
mVpp_se
Differential AC-coupled
225
—
1800
mVpp_se
250 MHz < f_IN < 750 MHz
Single-ended AC-coupled
100
—
3600
mVpp_se
f_IN < 250 MHz
Slew Rate^{2, 3}
SR
400
—
—
V/μs
Duty Cycle
DC
40
—
60
%
Input Capacitance
C_IN
—
0.3
—
pF
Input Resistance
R_IN
—
16
—
kΩ
Pulsed CMOS Input Buffer - DC Coupled (IN0, IN1, IN2)⁴
Input Frequency
f_IN
0.008
—
250
MHz
Input Voltage
V_IL
–0.2
—
0.4
V
V_IH
0.8
—
—
V
Slew Rate^{2, 3}
SR
400
—
—
V/μs
Duty Cycle
DC
Clock Input
40
—
60
%
Minimum Pulse Width
PW
Pulse Input
1.6
—
—
ns
Input Resistance
R_IN
—
8
—
kΩ
REFCLK (Applied to XA/XB)
Input Frequency Range
f_IN
Full operating range. Jitter
10
performance may be re-
duced.
—
200
MHz
Range for best jitter.
48
—
54
MHz
Input Single-ended Voltage
Swing
V_{IN_SE}
365
—
2000
mVpp_se
Input Differential Voltage Swing
V_{IN_DIFF}
365
—
2500
mVpp_diff
Slew Rate^{2, 3}
SR
Imposed for best jitter per-
400
—
formance
—
V/μs
Input Duty Cycle
DC
40
—
60
%
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