SI5341_16 Datasheet, PDF (25/53 Pages) Silicon Laboratories – Low-Jitter, 10 or 4-Output, Any-Frequency, Any-Output Clock Generator

Si5341/40 Rev D Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
Output Voltage Low^{1, 2, 3}
V_OL
V_DDO = 3.3 V
OUTx_CMOS_DRV=1 I_OL = 10 mA
—
—
V_DDO x 0.15
V
OUTx_CMOS_DRV=2 I_OL = 12 mA
—
—
OUTx_CMOS_DRV=3 I_OL = 17 mA
—
—
V_DDO = 2.5 V
OUTx_CMOS_DRV=1 I_OL = 6 mA
—
—
V_DDO x 0.15
V
OUTx_CMOS_DRV=2 I_OL = 8 mA
—
—
OUTx_CMOS_DRV=3 I_OL = 11 mA
—
—
V_DDO = 1.8 V
OUTx_CMOS_DRV=2 I_OL = 4 mA
—
—
V_DDO x 0.15
V
OUTx_CMOS_DRV=3 I_OL = 5 mA
—
—
LVCMOS Rise and Fall
tr/tf
Times³
(20% to 80%)
VDDO = 3.3V
VDDO = 2.5 V
VDDO = 1.8 V
—
400
600
ps
—
450
600
ps
—
550
750
ps
Notes:
1. Driver strength is a register programmable setting and stored in NVM. Options are OUTx_CMOS_DRV = 1, 2, 3. Refer to the
Family Reference Manual for more details on register settings.
2. I_OL/I_OH is measured at V_OL/V_OH as shown in the dc test configuration.
3. A series termination resistor (Rs) is recommended to help match the source impedance to a 50 W PCB trace. A 5 pF capacitive
load is assumed. The LVCMOS outputs were set to OUTx_CMOS_DRV = 3.
DC Test Configuration
IOL/IOH
IDDO
AC Test Configuration
Trace length 5 inches
499
50
DC Block
50 probe, scope
Zs
VOL/VOH
OUT
OUTb
50
4.7 pF
499
56
DC Block
50 probe, scope
4.7 pF
56
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