SI5341_16 Datasheet, PDF (24/53 Pages) Silicon Laboratories – Low-Jitter, 10 or 4-Output, Any-Frequency, Any-Output Clock Generator

Si5341/40 Rev D Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
Notes:
1. Output amplitude and common-mode settings are programmable through register settings and can be stored in NVM. Each out-
put driver can be programmed independently. The maximum LVDS single-ended amplitude can be up to 110 mV higher than the
TIA/EIA-644 maximum. Refer to the Si5341/40 Family Reference Manual for more suggested output settings. Not all combina-
tions of voltage amplitude and common mode voltages settings are possible.
OUTx
OUTxb
Vcm
Vcm
Vpp_se
Vpp_se
Vpp_ diff = 2* Vpp_se
2. Measured for 156.25 MHz carrier frequency. 100 mVpp sinewave noise added to VDDO = 3.3 V and noise spur amplitude meas-
ured.
3. Measured across two adjacent outputs, both in LVDS mode, with the victim running at 155.52 MHz and the aggressor at 156.25
MHz. Refer to application note, AN862: Optimizing Si534x Jitter Performance in Next Generation Internet Infrastructure Systems,
guidance on crosstalk minimization.
Table 5.6. LVCMOS Clock Output Specifications
(V_DD=1.8V ± 5%, V_DDA=3.3V ± 5%, V_DDO=1.8V ± 5%, 2.5V ± 5%, or 3.3V ± 5%, T_A= -40 to 85°C)
Parameter
Symbol
Test Condition
Min
Typ
Output Frequency
0.0001
—
Duty Cycle
DC
f_OUT < 100 MHz
48
—
100 MHz < f_OUT < 250 MHz
45
—
Output-to-Output Skew
T_SK
Outputs on same MultiSynth.
F_OUT = 156.25 MHz
—
30
Output Voltage High^{1, 2, 3}
V_OH
V_DDO = 3.3 V
OUTx_CMOS_DRV=1 I_{OH =} -10 mA V_DDO x 0.85
—
OUTx_CMOS_DRV=2 I_{OH =} -12 mA
—
OUTx_CMOS_DRV=3 I_{OH =} -17 mA
—
V_DDO = 2.5 V
OUTx_CMOS_DRV=1 I_{OH =} -6 mA V_DDO x 0.85
—
OUTx_CMOS_DRV=2 I_{OH =} -8 mA
—
OUTx_CMOS_DRV=3 I_{OH =} -11 mA
—
V_DDO = 1.8 V
OUTx_CMOS_DRV=2 I_{OH =} -4 mA V_DDO x 0.85
—
OUTx_CMOS_DRV=3 I_{OH =} -5 mA
—
Max
Units
250
MHz
52
%
55
140
ps
—
V
—
—
—
V
—
—
—
V
—
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