SI5341_16 Datasheet, PDF (34/53 Pages) Silicon Laboratories – Low-Jitter, 10 or 4-Output, Any-Frequency, Any-Output Clock Generator

6. Typical Application Schematic
Si5341/40 Rev D Data Sheet
Typical Application Schematic
161.1328125
MHz
Buffer
2x 161.1328125 MHz
LVDS
Buffer
133.33 MHz
Level
Translator
125 MHz
Buffer
Delay Line
Buffer
25 MHz
Clock
Generator
XA
XB
200 MHz
2.5V LVCMOS
Level
Translator
“Traditional Discrete” Clock Tree
2x 133.33 MHz
1.8V LVCMOS
3x 125 MHz
LVPECL
4x 125 MHz
3.3V LVCMOS
One Si5341 replaces:
3x crystal oscillators (XO)
2x buffers
1x Clock Generator
2x level translators
1x delay line
XA
25 MHz
XB
Si5341
“Clock Tree
On-a-Chip”
1x 161.1328125 MHz
LVDS
1x 161.1328125 MHz
LVDS
2x 133.33 MHz
1.8V LVCMOS
1x 125 MHz
LVPECL
1x 125 MHz
LVPECL
1x 125 MHz
LVPECL
2x 125 MHz
3.3V LVCMOS
2x 125 MHz
3.3V LVCMOS
2x 200 MHz
2.5V LVCMOS
2x 200 MHz
2.5V LVCMOS
Figure 6.1. Using the Si5341 to Replace a Traditional Clock Tree
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