SI5341_16 Datasheet, PDF (20/53 Pages) Silicon Laboratories – Low-Jitter, 10 or 4-Output, Any-Frequency, Any-Output Clock Generator

Si5341/40 Rev D Data Sheet
Electrical Specifications
Table 5.2. DC Characteristics
(V_DD=1.8V ± 5%, V_DDA=3.3V ± 5%, V_DDO=1.8V ± 5%, 2.5V ± 5%, or 3.3V ± 5%, T_A= -40 to 85°C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
Core Supply Current^{1, 2}
I_DD
Si5340/41
—
115
230
mA
I_DDA
Si5340/41
—
120
130
mA
Output Buffer Supply Current
I_DDOx
LVPECL Output³
—
22
26
mA
@ 156.25 MHz
LVDS Output³
—
15
18
mA
@ 156.25 MHz
3.3 V LVCMOS⁴ output
—
22
30
mA
@ 156.25 MHz
2.5 V LVCMOS⁴ output
—
18
23
mA
@ 156.25 MHz
1.8 V LVCMOS⁴ output
—
12
16
mA
@ 156.25 MHz
Total Power Dissipation^{1, 5}
P_d
Si5341
Si5340
—
880
1150
mW
—
680
875
mW
Note:
1. Si5341 test configuration: 7 x 2.5 V LVDS outputs enabled @ 156.25 MHz. Excludes power in termination resistors.
2. Si5340 test configuration: 4 x 2.5 V LVDS outputs enabled @ 156.25 MHz. Excludes power in termination resistors.
3. Differential outputs terminated into an ac-coupled 100 Ω load.
4. LVCMOS outputs measured into a 6-inch 50 W PCB trace with 5 pF load. The LVCMOS outputs were set to
OUTx_CMOS_DRV=3, which is the strongest driver setting. Refer to the Si5341/40 Family Reference Manual for more details on
register settings.
Differential Output Test Configuration
IDDO
OUT
OUTb
0. 1 uF
50
100
50
0. 1 uF
LVCMOS Output Test Configuration
IDDO
OUTa
OUTb
6 inch
50
5 pF
5. Detailed power consumption for any configuration can be estimated using ClockBuilderPro when an evaluation board (EVB) is not
available. All EVBs support detailed current measurements for any configuration.
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