SI5341_16 Datasheet, PDF (27/53 Pages) Silicon Laboratories – Low-Jitter, 10 or 4-Output, Any-Frequency, Any-Output Clock Generator

Si5341/40 Rev D Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
Jitter Generation Locked to Ex-
J_GEN
Integer Mode⁴
—
140
180
fs rms
ternal Clock³
12 kHz to 20 MHz
Fractional/DCO Mode⁵
—
160
210
fs rms
12 kHz to 20 MHz
J_PER
Derived from integrated
—
110
—
fs pk-pk
phase noise
J_CC
—
180
—
fs pk
J_PER
N = 10,000 cycles Integer
—
or Fractional Mode^{4, 5} .
J_CC
Measured in the time do-
—
main. Performance is limi-
ted by the noise floor of
the equipment.
7400
6700
—
fs pk-pk
—
fs pk
Jitter Generation Locked to Ex-
ternal XTAL
J_GEN
XTAL Frequency = 48 MHz
Integer Mode⁴
—
90
140
fs rms
12 kHz to 20 MHz
Fractional/DCO Mode⁵
—
115
170
fs rms
12 kHz to 20 MHz
J_PER
Derived from integrated
—
110
—
fs pk-pk
phase noise
J_CC
—
180
—
fs pk
J_PER
N = 10, 000 cycles Integer
—
or Fractional Mode.^{4, 5}
J_CC
Measured in the time do-
—
main. Performance is limi-
ted by the noise floor of
the equipment.
7400
6600
—
fs pk-pk
—
fs pk
XTAL Frequency = 25 MHz
J_GEN
Integer Mode⁴
115
140
fs rms
12 kHz to 20 MHz
Fractional Mode⁵
140
190
fs rms
12 kHz to 20 MHz
Notes:
1. PLL lock time is measured by first letting the PLL lock, then turning off the input clock, and then turning on the input clock. The
time from the first edge of the input clock being re-applied until LOL de-asserts is the PLL lock time.
2. Measured as time from valid V_DD and V_DD33 rails (90% of their value) to when the serial interface is ready to respond to com-
mands. Measured in SPI 4-wire mode, with SCLK @ 10 MHz.
3. Jitter generation test conditions f_IN = 100 MHz, f_OUT = 156.25 MHz LVPECL.
4. Integer mode assumes that the output dividers (Nn/Nd) are configured with an integer value.
5. Fractional and DCO modes assume that the output dividers (Nn/Nd) are configured with a fractional value and the feedback divid-
er is integer.
silabs.com | Smart. Connected. Energy-friendly.
Rev. 1.0 | 26