SI5341_16 Datasheet, PDF (31/53 Pages) Silicon Laboratories – Low-Jitter, 10 or 4-Output, Any-Frequency, Any-Output Clock Generator

Table 5.11. SPI Timing Specifications (3-Wire)
(V_DD=1.8V ± 5%, V_DDA=3.3V ± 5%, T_A= -40 to 85°C)
Parameter
SCLK Frequency
SCLK Duty Cycle
SCLK Period
Delay Time, SCLK Fall to SDO Turn-on
Delay Time, SCLK Fall to SDO Next-bit
Delay Time, CSb Rise to SDO Tri-State
Setup Time, CSb to SCLK
Hold Time, CSb to SCLK Rise
Setup Time, SDI to SCLK Rise
Hold Time, SDI to SCLK Rise
Delay Time Between Chip Selects (CSb)
Symbol
f_SPI
T_DC
T_C
T_D1
T_D2
T_D3
T_SU1
T_H1
T_SU2
T_H2
T_CS
Min
Typ
—
—
40
—
50
—
—
12.5
—
10
—
10
5
—
5
—
5
—
5
—
2
—
Si5341/40 Rev D Data Sheet
Electrical Specifications
Max
Units
20
MHz
60
%
—
ns
20
ns
15
ns
15
ns
—
ns
—
ns
—
ns
—
ns
—
T_C
SCLK
CSb
SDIO
T_SU1
T_SU2 T_H2
T_C
T_H1
T_D1
T_D2
T_CS
T_D3
Figure 5.3. 3-Wire SPI Serial Interface Timing
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