SI5341_16 Datasheet, PDF (7/53 Pages) Silicon Laboratories – Low-Jitter, 10 or 4-Output, Any-Frequency, Any-Output Clock Generator

Si5341/40 Rev D Data Sheet
Functional Description
3.3.2 Input Clocks (IN0, IN1, IN2)
A differential or single-ended clock can be applied at IN2, IN1, or IN0. The recommended input termination schemes are shown in the
figure below.
Standard AC Coupled Differential LVDS
50
3.3V, 2.5V
LVDS or
50
CML
INx
100
INxb
Si5341/40
Standard
Pulsed CMOS
Standard AC Coupled Differential LVPECL
50
3.3V, 2.5V
50
LVPECL
INx
100
INxb
Si5341/40
Standard
Pulsed CMOS
Standard AC Coupled Single Ended
50
3.3V, 2.5V, 1.8V
LVCMOS
INx
INxb
Si5341/40
Standard
Pulsed CMOS
Pulsed CMOS DC Coupled Single Ended
R1
50
Si5341/40
INx
Standard
3.3V, 2.5V, 1.8V
R2
LVCMOS
VDD
1.8 V
2.5 V
3.3 V
R1 (Ohm) R2 (Ohm)
324
665
511
475
634
365
INxb
Pulsed CMOS
Figure 3.3. Termination of Differential and LVCMOS Input Signals
silabs.com | Smart. Connected. Energy-friendly.
Rev. 1.0 | 6