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SI5341_16 Datasheet, PDF (11/53 Pages) Silicon Laboratories – Low-Jitter, 10 or 4-Output, Any-Frequency, Any-Output Clock Generator
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Si5341/40 Rev D Data Sheet
Functional Description
3.5.10 Synchronous/Asynchronous Output Disable Feature
Outputs can be configured to disable synchronously or asynchronously. The default state is synchronous output disable. In synchro-
nous disable mode the output will wait until a clock period has completed before the driver is disabled. This prevents unwanted runt
pulses from occurring when disabling an output. In asynchronous disable mode the output clock will disable immediately without waiting
for the period to complete.
3.5.11 Output Delay Control (t0-t4)
The Si5341/40 uses independent MultiSynth dividers (N0 - N4) to generate up to 5 unique frequencies to its 10 outputs through a cross-
point switch. By default all clocks are phase aligned. A delay path (t0 - t4) associated with each of these dividers is available for applica-
tions that need a specific output skew configuration. Each delay path is controlled by a register parameter call Nx_DELAY with a resolu-
tion of ~0.28 ps over a range of ~±9.14 ns. This is useful for PCB trace length mismatch compensation. After the delay controls are
configured, the soft reset bit SOFT_RST must be set high so that the output delay takes effect and the outputs are re-aligned.
÷N0
t0
÷N1
t1
÷N2
t2
÷N3
t3
÷N4
t4
÷R0
÷R1
÷R2
÷R3
÷R4
÷R5
÷R6
÷R7
÷R8
÷R9
VDDO0
OUT0
OUT0b
VDDO1
OUT1
OUT1b
VDDO2
OUT2
OUT2b
VDDO3
OUT3
OUT3b
VDDO4
OUT4
OUT4b
VDDO5
OUT5
OUT5b
VDDO6
OUT6
OUT6b
VDDO7
OUT7
OUT7b
VDDO8
OUT8
OUT8b
VDDO9
OUT9
OUT9b
Figure 3.7. Example of Independently Configurable Path Delays
All delay values are restored to their NVM programmed values after power-up or after a hard reset. Delay default values can be written
to the NVM allowing a custom delay offset configuration at power-up or after a hardware reset.
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