SI5341_16 Datasheet, PDF (30/53 Pages) Silicon Laboratories – Low-Jitter, 10 or 4-Output, Any-Frequency, Any-Output Clock Generator

Table 5.10. SPI Timing Specifications (4-Wire)
(V_DD=1.8V ± 5%, V_DDA=3.3V ± 5%, T_A= -40 to 85°C)
Parameter
SCLK Frequency
SCLK Duty Cycle
SCLK Period
Delay Time, SCLK Fall to SDO Active
Delay Time, SCLK Fall to SDO
Delay Time, CSb Rise to SDO Tri-State
Setup Time, CSb to SCLK
Hold Time, CSb to SCLK Rise
Setup Time, SDI to SCLK Rise
Hold Time, SDI to SCLK Rise
Delay Time Between Chip Selects (CSb)
Symbol
Min
Typ
f_SPI
—
—
T_DC
40
—
T_C
50
—
T_D1
—
12.5
T_D2
—
10
T_D3
—
10
T_SU1
5
—
T_H1
5
—
T_SU2
5
—
T_H2
5
—
T_CS
2
—
SCLK
CSb
SDI
SDO
TSU1
TD1
TC
TSU2
TH2
TD2
Figure 5.2. 4-Wire SPI Serial Interface Timing
Si5341/40 Rev D Data Sheet
Electrical Specifications
Max
Units
20
MHz
60
%
—
ns
18
ns
15
ns
15
ns
—
ns
—
ns
—
ns
—
ns
—
T_C
TH1
TCS
TD3
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