SI5341_16 Datasheet, PDF (16/53 Pages) Silicon Laboratories – Low-Jitter, 10 or 4-Output, Any-Frequency, Any-Output Clock Generator

Si5341/40 Rev D Data Sheet
Register Map
4. Register Map
The register map is divided into multiple pages where each page has 256 addressable registers. Page 0 contains frequently accessible
registers such as alarm status, resets, device identification, etc. Other pages contain registers that need less frequent access such as
frequency configuration, and general device settings. A high level map of the registers is shown in 4.2 High-Level Register Map. Refer
to the Si5340/41 Family Reference Manual for a complete list of register descriptions and settings.
4.1 Addressing Scheme
The device registers are accessible using a 16-bit address which consists of an 8-bit page address + 8-bit register address. By default
the page address is set to 0x00. Changing to another page is accomplished by writing to the ‘Set Page Address’ byte located at ad-
dress 0x01 of each page.
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