SI5341_16 Datasheet, PDF (5/53 Pages) Silicon Laboratories – Low-Jitter, 10 or 4-Output, Any-Frequency, Any-Output Clock Generator

Si5341/40 Rev D Data Sheet
Functional Description
3. Functional Description
The Si5340/41-D combines a wide band PLL with next generation MultiSynth technology to offer the industry's most versatile and high
performance clock generator. The PLL locks to either an external crystal between XA/XB or to an external clock connected to XA/XB
or IN0, 1, 2. A fractional or integer multiplier takes the selected input clock or cystal frequency up to a very high frequency that is then
divided by the MultiSynth output stage to any frequency in the range of 100 Hz to 1 GHz on each output. The MultiSynth stage can
divide by both integer and fractional values. The high-resolution fractional MultiSynth dividers enable true any-frequency input to any-
frequency on any of the outputs. The output drivers offer flexible output formats which are independently configurable on each of the
outputs. This clock generator is fully configurable via its serial interface (I²C/SPI) and includes in-circuit programmable non-volatile
memory.
3.1 Power-up and Initialization
Once power is applied, the device begins an initialization period where it downloads default register values and configuration data from
NVM and performs other initialization tasks. Communicating with the device through the serial interface is possible once this initializa-
tion period is complete. No clocks will be generated until the initialization is done. There are two types of resets available. A hard reset
is functionally similar to a device power-up. All registers will be restored to the values stored in NVM, and all circuits will be restored to
their initial state including the serial interface. A hard reset is initiated using the RSTb pin or by asserting the hard reset bit. A soft reset
bypasses the NVM download. It is simply used to initiate register configuration changes.
Power-Up
Hard Reset
bit asserted
RSTb
pin asserted
NVM download
Initialization
Soft Reset
bit asserted
Serial interface
ready
Figure 3.1. Si5341 Power-Up and Initialization
3.2 Frequency Configuration
The phase-locked loop is fully contained and does not require external loop filter components to operate. Its function is to phase lock to
the selected input and provide a common reference to the MultiSynth high-performance fractional dividers.
A crosspoint mux connects any of the MultiSynth divided frequencies to any of the outputs drivers. Additional output integer dividers
provide further frequency division by an even integer from 2 to (2^25)-2. The frequency configuration of the device is programmed by
setting the input dividers (P), the PLL feedback fractional divider (Mn/Md), the MultiSynth fractional dividers (Nn/Nd), and the output
integer dividers (R). Silicon Labs's ClockBuilder Pro configuration utility determines the optimum divider values for any desired input
and output frequency plan.
3.3 Inputs
The Si5340/41-D requires either an external crystal at its XA/XB pins or an external clock at XA/XB or IN0, 1, 2.
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