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SI5341_16 Datasheet, PDF (22/53 Pages) Silicon Laboratories – Low-Jitter, 10 or 4-Output, Any-Frequency, Any-Output Clock Generator
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Si5341/40 Rev D Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Note:
1. Voltage swing is specified as single-ended mVpp.
Vcm
Vcm
Vpp_se
Vpp_se
Min
Typ
Max
Units
Vpp_diff = 2*Vpp_se
2. Imposed for jitter performance.
3. Pulsed CMOS mode is intended primarily for single-ended LVCMOS input clocks < 1 MHz, which must be dc-coupled because
they have a duty cycle significantly less than 50%. A typical application example is a low frequency video frame sync pulse. Since
the input thresholds (VIL, VIH) of this buffer are non-standard (0.4 and 0.8 V, respectively), refer to the input attenuator circuit for
DC-coupled Pulsed LVCMOS in the Family Reference Manual. Otherwise, for standard LVCMOS input clocks, use the Standard
AC-Coupled, Single-ended input mode.
4. DC-coupled CMOS Input Buffer selection is not supported in ClockBuilder Pro for new designs. For single-ended LVCMOS inputs
to IN0,1,2 it is required to ac-couple into the differential input buffer.
Table 5.4. Control Input Pin Specifications
(VDD=1.8V ± 5%, VDDA=3.3V ± 5%, VDDS=3.3V ± 5%, 1.8V ± 5%, TA=-40 to 85°C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
Si5341 Control Input Pins (I2C_SEL, IN_SEL[1:0], RSTb, OEb, SYNCb, A1, SCLK, A0/CSb, FINC, FDEC, SDA/SDIO)
Input Voltage
VIL
—
—
0.3xVDDIO1
V
VIH
0.7xVDDIO1
—
—
V
Input Capacitance
CIN
—
2
—
pF
Input Resistance
RIN
—
20
—
kW
Minimum Pulse Width
TPW
RSTb, SYNCb, FINC, and
100
—
—
ns
FDEC
Frequency Update Rate
FUR
FINC and FDEC
—
—
1
MHz
Si5340 Control Input Pins (I2C_SEL, IN_SEL[1:0], RSTb, OEb, A1, SCLK, A0/CSb, SDA/SDIO)
Input Voltage
VIL
—
—
0.3xVDDIO1
V
VIH
0.7xVDDIO1
—
—
V
Input Capacitance
CIN
—
2
—
pF
Input Resistance
RIN
—
20
—
kW
Minimum Pulse Width
TPW
RSTb only
100
—
—
ns
Note:
1. VDDIO is determined by the IO_VDD_SEL bit. It is selectable as VDDA or VDD. Refer to the Family Reference Manual for more
details on register settings.
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