SI5341_16 Datasheet, PDF (42/53 Pages) Silicon Laboratories – Low-Jitter, 10 or 4-Output, Any-Frequency, Any-Output Clock Generator

Pin Name
A0/CSb
Pin Number
Si5341
Si5340
19
16
Control/Status
INTRb
12
33
RSTb
6
17
OEb
11
12
LOLb
47
—
—
27
LOS_XAXBb
—
28
SYNCb
5
—
FDEC
25
—
FINC
48
—
IN_SEL0
3
3
IN_SEL1
4
37
RSVD
20
—
21
—
55
—
56
—
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Pin Type¹
Si5341/40 Rev D Data Sheet
Pin Descriptions
Function
I
Address Select 0/Chip Select.² This pin functions as the hard-
ware controlled address A0 in I²C mode. In SPI mode, this pin
functions as the chip select input (active low). This pin is internally
pulled up by a ~20 kΩ resistor to the voltage selected by the
IO_VDD_SEL register bit.
O
Interrupt. ² This pin is asserted low when a change in device sta-
tus has occurred. This interrupt has a push pull output and should
be left unconnected when not in use.
I
Device Reset. ² Active low input that performs power-on reset
(POR) of the device. Resets all internal logic to a known state and
forces the device registers to their default values. Clock outputs
are disabled during reset. This pin is internally pulled up with a
~20 kΩ resistor to the voltage selected by the IO_VDD_SEL bit.
I
Output Enable.² This pin disables all outputs when held high.
This pin is internally pulled low and can be left unconnected when
not in use.
O
Loss Of Lock.² This output pin indicates when the DSPLL^™ is
locked (high) or out-of-lock (low). An external pull up or pull down
is not needed.
O
Loss Of Lock.³ This output pin indicates when the DSPLL is
locked (high) or out-of-lock (low). An external pull up or pull down
is not needed.
O
Loss Of Signal.³ This output pin indicates a loss of signal at the
XA/XB pins.
I
Output Clock Synchronization.² An active low signal on this pin
resets the output dividers for the purpose of re-aligning the output
clocks. For a tighter alignment of the clocks, a soft reset should be
applied. This pin is internally pulled up with a ~20 kΩ resistor to
the voltage selected by the IO_VDD_SEL bit and can be left un-
connected when not in use.
I
Frequency Decrement Pin.² This pin is used to step-down the
output frequency of a selected output. The affected output driver
and its frequency change step size is register configurable. This
pin is internally pulled low with a ~20 kΩ resistor and can be left
unconnected when not in use.
I
Frequency Increment Pin.² This pin is used to step-up the out-
put frequency of a selected output. The affected output and its fre-
quency change step size is register configurable. This pin is inter-
nally pulled low with a ~20 kΩ resistor and can be left unconnec-
ted when not in use.
I
Input Reference Select.² The IN_SEL[1:0] pins are used in the
I
manual pin controlled mode to select the active clock input. These
pins are internally pulled up with a ~20 kΩ resistor to the voltage
selected by the IO_VDD_SEL bit and can be left unconnected
when not in use.
—
Reserved. These pins are connected to the die. Leave discon-
nected.
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—
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Rev. 1.0 | 41