SI5341_16 Datasheet, PDF (17/53 Pages) Silicon Laboratories – Low-Jitter, 10 or 4-Output, Any-Frequency, Any-Output Clock Generator

4.2 High-Level Register Map
Table 4.1. High-Level Register Map
8-bit Page Address
00
01
02
03
16-Bit Address
8-bit Register Address Range
00
01
02-0A
0B-15
17-1B
1C
2C-E1
E2-E4
FE
01
08-3A
41-42
FE
01
02-05
08-2F
30
35-3D
3E
47-6A
6B-72
FE
01
02-37
0C
17
22
2D
38
39-58
59-62
63-94
FE
Si5341/40 Rev D Data Sheet
Register Map
Content
Revision IDs
Set Page Address
Device IDs
Alarm Status
INTR Masks
Reset controls
Alarm Configuration
NVM Controls
Device Ready Status
Set Page Address
Output Driver Controls
Output Driver Disable Masks
Device Ready Status
Set Page Address
XTAL Frequency Adjust
Input Divider (P) Settings
Input Divider (P) Update Bits
PLL Feedback Divider (M) Settings
PLL Feedback Divider (M) Update Bit
Output Divider (R) Settings
User Scratch Pad Memory
Device Ready Status
Set Page Address
MultiSynth Divider (N0-N4) Settings
MultiSynth Divider (N0) Update Bit
MultiSynth Divider (N1) Update Bit
MultiSynth Divider (N2) Update Bit
MultiSynth Divider (N3) Update Bit
MultiSynth Divider (N4) Update Bit
FINC/FDEC Settings N0-N4
Output Delay (Dt) Settings
Frequency Readback N0-N4
Device Ready Status
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