SI5341_16 Datasheet, PDF (35/53 Pages) Silicon Laboratories – Low-Jitter, 10 or 4-Output, Any-Frequency, Any-Output Clock Generator

7. Detailed Block Diagrams
Si5341/40 Rev D Data Sheet
Detailed Block Diagrams
IN_ SEL[1:0]
IN0
IN0b
IN1
IN1b
IN2
IN2b
3
÷P₀
÷P₁
÷P₂
XB
25-54 MHz
XTAL
XA
FB_IN
FB_ INb
÷ PXAXB
OSC
Zero Delay
Mode
÷P_fb
I2C_ SEL
SDA/ SDIO
A1/ SDO
SCLK
A 0/ CSb
SPI /
I²C
NVM
Status
Monitors
Si 5341
Clock
Generator
PLL
PD
÷
M_n
M_d
LPF
MultiSynth
÷
N_0n
N_0d
t₀
÷
N_1n
N_1d
t₁
÷
N_2n
N_2d
t₂
÷
N_3n
N_3d
t₃
÷
N_4n
N_4d
t₄
Frequency
Control
Dividers/
Drivers
÷R₀
÷R₁
÷R₂
÷R₃
÷R₄
÷R₅
÷R₆
÷R₇
÷R₈
÷R₉
VDDO0
OUT0
OUT0b
VDDO1
OUT1
OUT1b
VDDO2
OUT2
OUT2b
VDDO3
OUT3
OUT3b
VDDO4
OUT4
OUT4b
VDDO5
OUT5
OUT5b
VDDO6
OUT6
OUT6b
VDDO7
OUT7
OUT7b
VDDO8
OUT8
OUT8b
VDDO9
OUT9
OUT9b
Figure 7.1. Si5341 Block Diagram
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