SI5341_16 Datasheet, PDF (36/53 Pages) Silicon Laboratories – Low-Jitter, 10 or 4-Output, Any-Frequency, Any-Output Clock Generator

Si5341/40 Rev D Data Sheet
Detailed Block Diagrams
XB
25-54 MHz
XTAL
XA
IN0
IN0b
IN1
IN1b
IN2
IN2b
IN_ SEL[1:0]
FB_IN
FB_INB
÷P XAXB
OSC
÷P₀
÷P₁
÷P₂
Zero Delay
Mode
÷P_fb
4
2
1
Si 5340
Clock
Generator
PLL
LPF
PD
Md
M_n
÷
MultiSynth
÷
Nn0
N_d0
t₀
÷
N_n1
N_d1
t₁
÷
N_2n
N2d
t₂
÷
N3n
N3d
t₃
Dividers /
Drivers
÷R₀
÷R₁
÷R₂
÷R₃
Status
Monitors
SPI/
I² C
NVM
VDDO0
OUT0
OUT0b
VDDO1
OUT1
OUT1b
VDDO2
OUT2
OUT2b
VDDO3
OUT3
OUT3b
Figure 7.2. Si5340 Detailed Block Diagram
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