SI5341_16 Datasheet, PDF (26/53 Pages) Silicon Laboratories – Low-Jitter, 10 or 4-Output, Any-Frequency, Any-Output Clock Generator

Si5341/40 Rev D Data Sheet
Electrical Specifications
Table 5.7. Output Status Pin Specifications
(V_DD=1.8V ± 5%, V_DDA=3.3V ± 5%, V_DDS= 3.3V ± 5%, 1.8V ± 5%, T_A= -40 to 85°C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
Si5341/40 Status Output Pins (INTRb, SDA/SDIO)¹
Output Voltage
V_OH
I_OH = -2 mA
V_DDIO2 x
—
—
V
0.85
V_OL
I_OL = 2 mA
—
—
V_DDIO2x
V
0.15
Si5341 Status Output Pins (LOLb)
Output Voltage
V_OH
I_OH = -2 mA
V_DDIO2 x
—
—
V
0.85
V_OL
I_OL = 2 mA
—
—
V_DDIO2 x
V
0.15
Si5340 Status Output Pins (LOLb, LOS_XAXBb)
Output Voltage
V_OH
I_OH = -2 mA
V_DDS x 0.85
—
—
V
V_OL
I_OL = 2 mA
—
—
V_DDSx 0.15
V
Notes:
1. The V_OH specification does not apply to the open-drain SDA/SDIO output when the serial interface is in I2C mode or is unused
with I2C_SEL pulled high. V_OL remains valid in all cases.
2. V_DDIO is determined by the IO_VDD_SEL bit. It is selectable as V_DDA or V_DD. Refer to the Family Reference Manual for more
details on register settings.
Table 5.8. Performance Characteristics
(V_DD=1.8V ± 5%, V_DDA=3.3V ± 5%, T_A= -40 to 85°C)
Parameter
V_CO Frequency Range
PLL Loop Bandwidth
Initial Start-Up Time
PLL Lock Time¹
Output Delay Adjustment
POR² to Serial Interface Ready
Symbol
F_VCO
f_BW
t_START
t_ACQ
t_{DELAY_frac}
t_{DELAY_int}
t_RANGE
t_RDY
Test Condition
Time from power-up to
when the device gener-
ates clocks (Input Fre-
quency >48 MHz)
f_IN = 19.44 MHz
f_VCO = 14 GHz
Delay is controlled by the
MultiSynth
Min
13.5
—
—
15
—
—
—
—
Typ
—
1.0
30
—
0.28
71.4
±9.14
—
Max
14.4
—
45
150
—
—
—
15
Units
GHz
MHz
ms
ms
ps
ps
ns
ms
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