SI5341_16 Datasheet, PDF (43/53 Pages) Silicon Laboratories – Low-Jitter, 10 or 4-Output, Any-Frequency, Any-Output Clock Generator

Si5341/40 Rev D Data Sheet
Pin Descriptions
Pin Name
NC
Power
VDD
VDDA
VDDS
VDDO0
VDDO1
VDDO2
VDDO3
VDDO4
VDDO5
VDDO6
VDDO7
VDDO8
VDDO9
GND PAD
Note:
Pin Number
Si5341
Si5340
—
22
32
21
46
32
60
39
—
40
13
8
—
9
—
26
22
18
26
23
29
29
33
34
36
—
40
—
43
—
49
—
52
—
57
—
Pin Type¹
Function
—
No Connect. These pins are not connected to the die. Leave dis-
connected.
P
Core Supply Voltage. The device core operates from a 1.8 V
supply. A 1.0 µf bypass capacitor is recommended.
P
Core Supply Voltage 3.3 V. This core supply pin requires a 3.3 V
power source. A 1.0 µf bypass capacitor is recommended.
P
P
Status Output Voltage. The voltage on this pin determines the
V_OL/V_OH on LOLb and LOS_XAXBb status output pins. A 0.1 µf to
1.0 µf bypass capacitor is recommended.
P
Output Clock Supply Voltage 0–9. Supply voltage (3.3 V, 2.5 V,
1.8 V) for OUTx, OUTx outputs. See the Si5341/40 Family Refer-
P
ence Manual for power supply filtering recommendations. Leave
P
VDDO pins of unused output drivers unconnected. An alternate
option is to connect the VDDO pin to a power supply and disable
P
the output driver to minimize current consumption.
P
P
P
P
P
P
P
Ground Pad This pad provides electrical and thermal connection
to ground and must be connected for proper operation. Use as
many vias as practical and keep the via length to an internal
ground plan as short as possible.
1. I = Input, O = Output, P = Power.
2. The IO_VDD_SEL control bit (0x0943 bit 0) selects 3.3 V or 1.8 V operation.
3. The voltage on the VDDS pin(s) determines 3.3 V or 1.8 V operation.
4. Refer to the Family Reference Manual for more information on register setting names.
5. All status pins except I2C and SPI are push-pull.
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