SI5341_16 Datasheet, PDF (28/53 Pages) Silicon Laboratories – Low-Jitter, 10 or 4-Output, Any-Frequency, Any-Output Clock Generator

Table 5.9. I²C Timing Specifications (SCL,SDA)
Parameter
Symbol
Test Condition
SCL Clock Frequency
Hold Time (Repeated)
START Condition
Low Period of the SCL Clock
HIGH Period of the SCL
Clock
Set-up Time for a Repeated
START Condition
Data Hold Time
Data Set-up Time
Rise Time of Both SDA and
SCL Signals
Fall Time of Both SDA and
SCL Signals
Set-up Time for STOP Con-
dition
Bus Free Time between a
STOP and START Condition
Data Valid Time
Data Valid Acknowledge
Time
f_SCL
t_HD:STA
t_LOW
t_HIGH
t_SU:STA
t_HD:DAT
t_SU:DAT
t_r
t_f
t_SU:STO
t_BUF
t_VD:DAT
t_VD:ACK
Standard Mode
100 kbps
Min
Max
—
100
4.0
—
4.7
—
4.0
—
4.7
—
100
—
250
—
—
1000
—
300
4.0
—
4.7
—
—
3.45
—
3.45
Si5341/40 Rev D Data Sheet
Electrical Specifications
Fast Mode
400 kbps
Min
Max
—
400
0.6
—
1.3
—
0.6
—
0.6
—
100
—
100
—
20
300
—
300
0.6
—
1.3
—
—
0.9
—
0.9
Units
kHz
μs
μs
μs
μs
ns
ns
ns
ns
μs
μs
μs
μs
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