C515A_9708 Datasheet, PDF (84/182 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

On-Chip Peripheral Components
C515A
Contents
of
Timer 2
Timer Count = FFFF _H
Timer Count =
Compare Value
Timer Count = Reload Value
Interrupt can be generated
on overflow
Compare
Output
(P1.x/CCx)
MCT01906
Interrupt can be generated
on compare-match
Figure 6-17
Function of Compare Mode 0
6.2.2.3.2 Modulation Range in Compare Mode 0
Generally it can be said that for every PWM generation in compare mode 0 with n-bit wide compare
registers there are 2ⁿ different settings for the duty cycle. Starting with a constant low level (0%duty
cycle) as the first setting, the maximum possible duty cycle then would be :
(1 - 1/2ⁿ) x 100%
This means that a variation of the duty cycle from 0% to real 100% can never be reached if the
compare register and timer register have the same length. There is always a spike which is as long
as the timer clock period.
This “spike“ may either appear when the compare register is set to the reload value (limiting the
lower end of the modulation range) or it may occur at the end of a timer period. In a timer 2/CCx
register configuration in compare mode 0 this spike is divided into two halves: one at the beginning
when the contents of the compare register is equal to the reload value of the timer; the other half
when the compare register is equal to the maximum value of the timer register (here: FFFFH).
Please refer to figure 6-18 where the maximum and minimum duty cycle of a compare output signal
is illustrated. Timer 2 is incremented with the machine clock (fosc/12), thus at 24-MHz operating
frequency, these spikes are both approx. 250 ns long.
Semiconductor Group
6-33
1997-08-01