C515A_9708 Datasheet, PDF (117/182 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

On-Chip Peripheral Components
C515A
6.4.4
A/D Conversion Timing
An A/D conversion is internally started by writing into the SFR ADDATL with dummy data. A write
to SFR ADDATL will start a new conversion even if a conversion is currently in progress. The
conversion begins with the next machine cycle, and the BSY flag in SFR ADCON0 will be set.
The A/D conversion procedure is divided into three parts :
– Sample phase (t_S), used for sampling the analog input voltage.
– Conversion phase (t_CO), used for the real A/D conversion (including calibration).
– Write result phase (t_WR), used for writing the conversion result into the ADDAT registers.
The total A/D conversion time is defined by t_ADCC which is the sum of the three phase times t_S and
t_CO. The duration of the three phases of an A/D conversion is specified by its specific timing
parameter as shown in figure 6-33.
Internal start of
AD conversion
Result is written
into ADDAT
BSY Bit
Sample
Phase
t_S
Conversion Phase
t _CO
t _ADCC
A/D Conversion Cycle Time
t _ADCC = t _S + t _CO
t _WR
Write
Result
Phase
t _WR = t _IN
MCT03265
Selected
Divider Ratio
÷4
÷8
t_S
t_CO
t_ADCC
8 x t_IN
16 x t_IN
40 x t_IN
80 x t_IN
48 x t_IN
96 x t_IN
Figure 6-33
A/D Conversion Timing
Sample Time t_S :
During this time the internal capacitor array is connected to the selected analog input channel and
is loaded with the analog voltage to be converted. The analog voltage is internally fed to a voltage
comparator. With beginning of the sample phase the BSY bit in SFR ADCON0 is set.
Conversion Time t_CO :
During the conversion time the analog voltage is converted into a 10-bit digital value using the
successive approximation technique with a binary weighted capacitor network. During an A/D
conversion also a calibration takes place. During this calibration alternating offset and linearity
calibration cycles are executed (see also section 6.4.5). At the end of the conversion time the BSY
bit is reset and the IADC bit in SFR IRCON is set indicating an A/D converter interrupt condition.
Semiconductor Group
6-66
1997-08-01