C515A_9708 Datasheet, PDF (153/182 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

Power Saving Modes
C515A
9.4 Software Power Down Mode
In the software power down mode, the RC osciillator and the on-chip oscillator which operates with
the XTAL pins is stopped. Therefore, all functions of the microcontroller are stopped and only the
contents of the on-chip RAM, XRAM and the SFR's are maintained. The port pins, which are
controlled by their port latches, output the values that are held by their SFR's. The port pins which
serve the alternate output functions show the values they had at the end of the last cycle of the
instruction which initiated the software power down mode. ALE and PSEN hold at logic low level
(see table 9-1).
In the software power down mode of operation, V_CC can be reduced to minimize power
consumption. It must be ensured, however, that is V_CC not reduced before the software power down
mode is invoked, and that V_CC is restored to its normal operating level before the software power
down mode is terminated.
The software power down mode can be left either by an active reset signal or by a low signal at the
P3.2/INT0 pin. Using reset to leave software power down mode puts the microcontroller with its
SFRs into the reset state. Using the P3.2/INT0 pin for software power down mode exit starts the RC
oscillator and the on-chip oscillator and maintains the state of the SFRs, which has been frozen
when software power down mode is entered. Leaving software power down mode should not be
done before V_CC is restored to its nominal operating level.
9.4.1 Invoking Software Power Down Mode
The software power down mode is entered by two consecutive instructions. The first instruction has
to set the flag bit PDE (PCON.1) and must not set bit PDS (PCON.6), the following instruction has
to set the start bit PDS (PCON.6) and must not set bit PDE (PCON.1). The hardware ensures that
a concurrent setting of both bits, PDE and PDS, does not initiate the software power down mode.
Bits PDE and PDS will automatically be cleared after having been set and the value shown by
reading one of these bits is always 0. This double instruction is implemented to minimize the chance
of unintentionally entering the software power down mode which could possibly ”freeze” the chip's
activity in an undesired status.
PCON is not a bit-addressable register, so the above mentioned sequence for entering the software
power down mode is obtained by byte-handling instructions, as shown in the following example:
ORL
ORL
PCON,#00000010B
PCON,#01000000B
;set bit PDE, bit PDS must not be set
;set bit PDS, bit PDE must not be set, enter power down
The instruction that sets bit PDS is the last instruction executed before going into software power
down mode. When the double instruction sequence shown above is used, the software power down
mode can only be left by a reset operation. If the external wake-up from power down capability has
also to be used, its function must be enabled using the following instruction sequence prior to
executing the double instruction sequence shown above.
ORL
ORL
ANL
SYSCON,#00010000B
PCON1,#80H
SYSCON,#11101111B
;set RMAP
;enable external wake-up from software power down by
;setting EWPD
;reset RMAP (for future SFR accesses)
Setting EWPD automatically disables all interrupts still maintaining all actual values of the interrupt
enable bits.
Note : Before entering the power down mode, an A/D conversion in progress must be stopped.
Semiconductor Group
9-6
1997-08-01