C515A_9708 Datasheet, PDF (116/182 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

On-Chip Peripheral Components
C515A
6.4.3
A/D Converter Clock Selection
The ADC uses two clock signals for operation : the conversion clock f_ADC (=1/t_ADC) and the input
clock f_IN (=1/t_IN). Both clock signals are derived from the C515A system clock f_OSC which is applied
at the XTAL pins via the ADC clock prescaler as shown in figure 6-32. The input clock f_IN is always
f_OSC/2 while the conversion clock must be adapted to the input clock f_OSC. The conversion clock
is limited to a maximum frequency of 2 MHz. Therefore, the ADC clock prescaler must be
programmed to a value which assures that the conversion clock does not exceed 2 MHz. The
prescaler ratio is selected by the bit ADCL of SFR ADCON1.
The table in figure 6-32 shows the prescaler ratio which must be selected for typical system clock
rates. Up to 16 MHz system clock the prescaler ratio 4 is selected. Using a system clock greater
than 16 MHz (max. 24 MHz) the prescaler ratio of at least 8 must be selected. The prescaler ratio
8 is recommended when the input impedance of the analog source is to high to reach the maximum
accuracy.
f _OSC / 2
ADCL
4
MUX
Conversion Clock f _ADC
8
Clock Prescaler
Input Clock f _IN
A/D
Converter
Conditions: f _{ADC max} ^< 2 MHz
f _IN =
f _{OSC =}
2
1
2 t _CLCL
MCS03264
MCU System Clock f_IN
Rate (f_OSC)
[MHz]
3.5 MHz
1.75
12 MHz
6
16 MHz
8
18 MHz
9
24 MHz
12
Prescaler
Ratio
÷4
÷4
÷4
÷8
÷8
f_ADC [MHz] ADCL
.438
0
1.5
0
2
0
1.125
1
1.5
1
Figure 6-32
A/D Converter Clock Selection
The duration of an A/D conversion is a multiple of the period of the f_IN clock signal. The calculation
of the A/D conversion time is shown in the next section.
Semiconductor Group
6-65
1997-08-01