C515A_9708 Datasheet, PDF (24/182 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

Memory Organization
C515A
3.4.2 Accesses to XRAM using the DPTR (16-bit Addressing Mode)
The XRAM can be accessed by two read/write instructions, which use the 16-bit DPTR for indirect
addressing. These instructions are :
– MOVX A, @DPTR (Read)
– MOVX @DPTR, A (Write)
For accessing the XRAM, the effective address stored in DPTR must be in the range of FC00H to
FFFFH.
3.4.3 Accesses to XRAM using the Registers R0/R1 (8-bit Addressing Mode)
The 8051 architecture provides also instructions for accesses to external data memory range which
use only an 8-bit address (indirect addressing with registers R0 or R1). The instructions are:
MOVX
MOVX
A, @Ri
@Ri, A
(Read)
(Write)
A special page register is implemented in the C515A to provide the possibility of accessing the
XRAM also with the MOVX @Ri instructions, i.e. XPAGE serves the same function for the XRAM as
Port 2 for external data memory.
Special Function Register XPAGE (Address 91H)
Reset Value : 00H
Bit No. MSB
LSB
7
6
5
4
3
2
1
0
91H
.7
.6
.5
.4
.3
.2
.1
.0 ^XPAGE
Bit
XPAGE.7-0
Function
XRAM controller high address
XPAGE.7-0 is the address part A15-A8 when 8-bit MOVX instructions are
used to access internal XRAM.
Figures 3-2 to 3-4 show the dependencies of XPAGE- and Port 2 - addressing in order to explain
the differences in accessing XRAM, ext. RAM or what is to do when Port 2 is used as an I/O port.
Semiconductor Group
3-5
1997-08-01