C515A_9708 Datasheet, PDF (28/182 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

Memory Organization
C515A
The register XPAGE provides the upper address byte for accesses to XRAM with MOVX @Ri
instructions. If the address formed by XPAGE and Ri points outside the XRAM address range, an
external access is performed. For the C515A the content of XPAGE must be FCH - FFH in order to
use the XRAM.
The software has to distinguish two cases, if the MOVX @Ri instructions with paging shall be used :
a) Access to XRAM :
The upper address byte must be written to XPAGE or P2;
both writes select the XRAM address range.
b) Access to external memory : The upper address byte must be written to P2; XPAGE will be
automatically loaded with the same address in order to deselect
the XRAM.
3.4.4 Reset Operation of the XRAM
The contents of the XRAM are not affected by a reset. After power-up the contents are undefined,
while they remain unchanged during and after a reset as long as the power supply is not turned off.
If a reset occurs during a write operation to XRAM, the content of a XRAM memory location
depends on the cycle in which the active reset signal is detected (MOVX is a 2-cycle instruction):
Reset during 1st cycle : The new value will not be written to XRAM. The old value is not affected.
Reset during 2nd cycle : The old value in XRAM is overwritten by the new value.
3.4.5 Behaviour of Port 0 and Port 2
The behaviour of port 0 and port 2 during a MOVX access depends on the control bits in register
SYSCON and on the state of pin EA. The table 3-1 lists the various operating conditions. It shows
the following characteristics:
a) Use of P0 and P2 pins during the MOVX access.
Bus : The pins work as external address/data bus. If (internal) XRAM is accessed, the data
written to the XRAM/ can be seen on the bus in debug mode.
I/0 : The pins work as Input/Output lines under control of their latch.
b) Activation of the RD and WR pin during the access.
c) Use of internal (XRAM) or external XDATA memory.
The shaded areas describe the standard operation as each C500 microcontroller device without on-
chip XRAM behaves.
Semiconductor Group
3-9
1997-08-01