C515A_9708 Datasheet, PDF (130/182 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

Interrupt System
C515A
The timer 2 interrupt is generated by the logical OR of bit TF2 in register T2CON and bit EXF2 in
register IRCON. Neither of these flags is cleared by hardware when the service routine is vectored
to. In fact, the service routine may have to determine whether it was TF2 or EXF2 that generated the
interrupt, and the bit will have to be cleared by software.
The A/D converter interrupt is generated by IADC bit in register IRCON. If an interrupt is
generated, in any case the converted result in ADDAT is valid on the first instruction of the interrupt
service routine. lf continuous conversion is established, IADC is set once during each conversion.
lf an A/D converter interrupt is generated, flag IADC will have to be cleared by software.
The external interrupts 4 to 6 (INT4, INT5, INT6) are positive transition-activated. The flags that
actually generate these interrupts are bits IEX4, IEX5, and IEX6 in register IRCON. In addition,
these flags will be set if a compare event occurs at the corresponding output pin P1.1/ INT4/CC1,
P1.2/INT5/CC2, and P1.3/INT6/CC3, regardless of the compare mode established and the
transition at the respective pin. When an interrupt is generated, the flag that generated it is cleared
by the on-chip hardware when the service routine is vectored to.
All of these interrupt request bits that generate interrupts can be set or cleared by software, with the
same result as if they had been set or cleared by hardware. That is, interrupts can be generated or
pending interrupts can be cancelled by software. The only exceptions are the request flags IE0 and
lE1. lf the external interrupts 0 and 1 are programmed to be level-activated, IE0 and lE1 are
controlled by the external source via pin INT0 and INT1, respectively. Thus, writing a one to these
bits will not set the request flag IE0 and/or lE1. In this mode, interrupts 0 and 1 can only be
generated by software and by writing a 0 to the corresponding pins INT0 (P3.2) and INT1 (P3.3),
provided that this will not affect any peripheral circuit connected to the pins.
Semiconductor Group
7-9
1997-08-01