C515A_9708 Datasheet, PDF (118/182 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

On-Chip Peripheral Components
C515A
Write Result Time t_WR :
At the result phase the conversion result is written into the ADDAT registers.
Figure 6-34 shows how an A/D conversion is embedded into the microcontroller cycle scheme
using the relation 12 x t _IN = 1 instruction cycle. It also shows the behaviour of the busy flag (BSY)
and the interrupt flag (IADC) during an A/D conversion.
Prescaler
Selection
MOV ADDATL,
#0
1 Instruction Cycle
Write Result Cycle
MOV A, ADDATL
ADCL = 0
X-1 X 1 2 3 4 5 6 7 8 9 10 11 12
ADCL = 1
X-1 X 1 2 3 4 5
Start of A / D
conversion Cycle
t _ADCC
15 16 17 18 19 20
Start of next conversion
(in continuous mode)
BSY Bit
A / D Conversion Cycle
Write
ADDAT
Cont. conv.
Single conv.
ADCL = 0 _{IADC Bit}
ADCL = 1 _{IADC Bit}
First Instr. of an
Interrupt Routine
First Instr. of an
Interrupt Routine
MCT03266
Figure 6-34
A/D Conversion Timing in Relation to Processor Cycles
Depending on the selected prescaler ratio (see figure 6-32), two different relationships between
machine cycles and A/D conversion are possible. The A/D conversion is always started with the
beginning of a processor cycle when it has been started by writing SFR ADDATL with dummy data
or after an high-to-low transition has been detcted at P4.0 / ADST. The ADDATL write operation
may take one or two machine cycles. In figure 6-34, the instruction MOV ADDATL,#00 starts the
A/D conversion (machine cycle X-1 and X). The total A/D conversion is finished with the end of the
8th or 16th machine cycle after the A/D conversion start. In the next machine cycle the conversion
result is written into the ADDAT registers and can be read in the same cycle by an instruction (e.g.
Semiconductor Group
6-67
1997-08-01