C515A_9708 Datasheet, PDF (60/182 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

On-Chip Peripheral Components
C515A
6.1.2.4 Detailed Output Driver Circuitry
In fact, the pullups mentioned before and included in figure 6-2, 6-4 and 6-5 are pullup
arrangements.
Figure 6-7 shows the detailed output driver (pullup arrangement) circuit of the the port 1 and 3 to 5
port lines. The basic circuitry of these ports is shown in figure 6-4. The pullup arrangement of these
port lines has one n-channel pulldown FET and three pullup FETs:
Delay = 1 State
=1
1
p1
Q
Input Data
(Read Pin)
n1
V_SS
=1
V_CC
p2
p3
Port
Pin
=1
MCS03230
Figure 6-7
Driver Circuit of Ports 1, 3 to 6
– The pulldown FET n1 is of n-channel type. It is a very strong driver transistor which is capable
of sinking high currents (I_OL); it is only activated if a "0" is programmed to the port pin. A short
circuit to V_CC must be avoided if the transistor is turned on, since the high current might destroy
the FET. This also means that no “0“ must be programmed into the latch of a pin that is used
as input.
– The pullup FET p1 is of p-channel type. It is activated for one state (S1) if a 0-to-1 transition
is programmed to the port pin, i.e. a "1" is programmed to the port latch which contained a "0".
The extra pullup can drive a similar current as the pulldown FET n1. This provides a fast
transition of the logic levels at the pin.
– The pullup FET p2 is of p-channel type. It is always activated when a "1" is in the port latch,
thus providing the logic high output level. This pullup FET sources a much lower current than
p1; therefore the pin may also be tied to ground, e.g. when used as input with logic low input
level.
– The pullup FET p3 is of p-channel type. It is only activated if the voltage at the port pin is
higher than approximately 1.0 to 1.5 V. This provides an additional pullup current if a logic
high level shall be output at the pin (and the voltage is not forced lower than approximately
1.0 to 1.5 V). However, this transistor is turned off if the pin is driven to a logic low level, e.g
when used as input. In this configuration only the weak pullup FET p2 is active, which sources
Semiconductor Group
6-9
1997-08-01