C515A_9708 Datasheet, PDF (23/182 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

Memory Organization
C515A
After a reset operation, bit XMAP0 is set. This means that the accesses to XRAM are generally
disabled. In this case, all accesses using MOVX instructions within the address range of FC00H to
FFFFH generate external data memory bus cycles. When XMAP0 is cleared, the access to XRAM
is enabled and all accesses using MOVX instructions with an address in the range of FC00H to
FFFFH will access the internal XRAM.
Bit XMAP0 is hardware protected. If it is cleared once (XRAM access enabled) it cannot be set by
software. Only a reset operation will set the XMAP0 bit again. This hardware protection mechanism
is done by an asymmetric latch at XMAP0 bit. An unintentional disabling of XRAM could be
dangerous since indeterminate values could be read from the external bus. To avoid this the
XMAP0 bit is forced to '1' only by a reset operation. Additionally, during reset an internal capacitor
is charged. So the reset state is a disabled XRAM. Because of the charge time of the capacitor,
XMAP0 bit once written to '0' (that is, discharging the capacitor) cannot be set to '1' again by
software. On the other hand any distortion (software hang up, noise,...) is not able to charge this
capacitor, too. That is, the stable status is XRAM enabled.
The clear instruction for the XMAP0 bit should be integrated in the program initialization routine
before XRAM is used. In extremely noisy systems the user may have redundant clear instructions.
Semiconductor Group
3-4
1997-08-01