C515A_9708 Datasheet, PDF (141/182 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

Fail Safe Mechanisms
C515A
8.1.2 Watchdog Timer Control / Status Flags
The watchdog timer is controlled by two control flags (located in SFR IEN0 and IEN1) and one
status flags (located in SFR IP0).
Special Function Register IEN0 (Address A8H)
Special Function Register IEN1 (Address B8H)
Special Function Register IP0 (Address A9H)
Reset Value : 00H
Reset Value : 00H
Reset Value : 00H
MSB
AF_H
AE_H AD_H
AC_H
AB_H AA_H
LSB
A9_H A8_H
A8H EAL WDT ET2 ES ET1 EX1 ET0 EX0 IEN0
BF_H BE_H
B8H EXEN2 SWDT
BD_H
EX6
BC_H BB_H BA_H
EX5 EX4 EX3
B9_H B8_H
EX2 EADC
IEN1
Bit No. 7
6
5
4
3
2
1
0
A9H OWDS WDTS IP0.5 IP0.4 IP0.3 IP0.2 IP0.1 IP0.0 IP0
Bit
WDT
SWDT
WDTS
The shaded bits are not used for fail save control.
Function
Watchdog timer refresh flag.
Set to initiate a refresh of the watchdog timer. Must be set directly
before SWDT is set to prevent an unintentional refresh of the
watchdog timer.
Watchdog timer start flag.
Set to activate the Watchdog Timer. When directly set after setting
WDT, a watchdog timer refresh is performed.
Watchdog timer status flag.
Set by hardware when a watchdog Timer reset occured. Can be
cleared and set by software.
Semiconductor Group
8-3
1997-08-01