C515A_9708 Datasheet, PDF (42/182 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

External Bus Interface
C515A
condition is stored internally. After each 16th data byte the cumulated verify result (pass or fail) of
the last 16 verify operations is output at P3.5. This means that P3.5 stays at static level (low for fail
and high for pass) during the 16 bytes are checked. In ROM verification mode 2, the C515A-4R
must be provided with a system clock at the XTAL pins
Figure 4-5 shows an application example of an external circuitry which allows to verify a protected
ROM inside the C515A-4R in ROM verification mode 2. With RESET going inactive, the C515A-4R
starts the ROM verify sequence. Its ALE is clocking a 15-bit address counter. This counter
generates the addresses for an external EPROM which is programmed with the contents of the
internal (protected) ROM. The verify detect logic typically displays the pass/fail information of the
verify operation. P3.5 can be latched with the falling edge of ALE.
When the last byte of the internal ROM has been handled, the C515A-4R starts generating a PSEN
signal. This signal or the CY signal of the address counter indicate to the verify detect logic the end
of the internal ROM verification.
Figure 4-5
ROM Verification Mode 2 - External Circuitry Example
Semiconductor Group
4-8
1997-08-01