C515A_9708 Datasheet, PDF (22/182 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

Memory Organization
C515A
3.4 XRAM Operation
The XRAM in the C515A is a memory area that is logically located at the upper end of the external
data memory space, but is integrated on the chip. Because the XRAM is used in the same way as
external data memory the same instruction types (MOVX) must be used for accessing the XRAM.
3.4.1 XRAM Controller Access Control
Two bits in SFR SYSCON, XMAP0 and XMAP1, control the accesses to XRAM . XMAP0 is a
general access enable/disable control bit and XMAP1 controls the external signal generation during
XRAM accesses.
Special Function Register SYSCON (Address B1H)
Reset Value : XX10XX01B
Bit No. MSB
7
B1H
–
6
5
4
3
– EALE RMAP –
LSB
2
1
0
– XMAP1 XMAP0 SYSCON
The functions of the shaded bits are not described in this section.
Bit
XMAP1
XMAP0
–
Function
XRAM visible access control
Control bit for RD/WR signals during XRAM accesses. If addresses are
outside the XRAM address range or if XRAM is disabled, this bit has no
effect.
XMAP1 = 0 : The signals RD and WR are not activated during accesses to
the XRAM.
XMAP1 = 1 : Ports 0, 2 and the signals RD and WR are activated during
accesses to XRAM. In this mode, address and data
information during XRAM accesses are visible externally.
Global XRAM controller access enable/disable control
XMAP0 = 0 : The access to XRAM is enabled.
XMAP0 = 1 : The access to XRAM is disabled (default after reset). All
MOVX accesses are performed via the external bus. Further,
this bit is hardware protected.
Reserved bits for future use. Read by CPU returns undefined values.
When bit XMAP1 in SFR SYSCON is set, during all accesses to XRAM RD and WR become active
and port 0 and 2 drive the actual address/data information which is read/written from/to XRAM . This
feature allows to check the internal data transfers to XRAM. When port 0 and 2 are used for I/O
purposes, the XMAP1 bit should not be set. Otherwise the I/O function of the port 0 and port 2 lines
is interrupted.
Semiconductor Group
3-3
1997-08-01