C515A_9708 Datasheet, PDF (134/182 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

Interrupt System
C515A
7.3 How Interrupts are Handled
The interrupt flags are sampled at S5P2 in each machine cycle. The sampled flags are polled during
the following machine cycle. If one of the flags was in a set condition at S5P2 of the preceeding
cycle, the polling cycle will find it and the interrupt system will generate a LCALL to the appropriate
service routine, provided this hardware-generated LCALL is not blocked by any of the following
conditions:
1. An interrupt of equal or higher priority is already in progress.
2. The current (polling) cycle is not in the final cycle of the instruction in progress.
3. The instruction in progress is RETI or any write access to registers IEN0 and IEN1 or IP0/IP1.
Any of these three conditions will block the generation of the LCALL to the interrupt service routine.
Condition 2 ensures that the instruction in progress is completed before vectoring to any service
routine. Condition 3 ensures that if the instruction in progress is RETI or any write access to
registers IEN0/IEN1 or IP0/IP1, then at least one more instruction will be executed before any
interrupt is vectored to; this delay guarantees that changes of the interrupt status can be observed
by the CPU.
The polling cycle is repeated with each machine cycle, and the values polled are the values that
were present at S5P2 of the previous machine cycle. Note that if any interrupt flag is active but not
being responded to for one of the conditions already mentioned, or if the flag is no longer active
when the blocking condition is removed, the denied interrupt will not be serviced. In other words, the
fact that the interrupt flag was once active but not serviced is not remembered. Every polling cycle
interrogates only the pending interrupt requests.
The polling cycle/LCALL sequence is illustrated in figure 7-3.
C1
S5P2
Interrupt
is latched
C2
C3
C4
Interrupts
are polled
Long Call to Interrupt
Vector Address
Figure 7-3
Interrupt Response Timing Diagram
C5
Interrupt
Routine
MCT01859
Semiconductor Group
7-13
1997-08-01