C515A_9708 Datasheet, PDF (50/182 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

Reset / System Clock
C515A
5.5 System Clock Output
For peripheral devices requiring a system clock, the C515A provides a clock output signal derived
from the oscillator frequency as an alternate output function on pin P1.6/CLKOUT. lf bit CLK is set
(bit 6 of special function register ADCON0), a clock signal with 1/12 of the oscillator frequency is
gated to pin P1.6/CLKOUT. To use this function the port pin must be programmed to a one (1),
which is also the default after reset.
Special Function Register ADCON0 (Address D8H)
Reset Value : 00H
Bit No.
D8H
MSB
DFH
BD
DEH DDH
CLK ADEX
DCH DBH
BSY ADM
DAH
MX2
D9H
MX1
LSB
D8H
MX0
ADCON0
The shaded bits are not used for clock output control.
Bit
Function
CLK
Clockout enable bit
When set, pin P1.6/CLKOUT outputs the system clock which is 1/12 of the
oscillator frequency.
The system clock is high during S3P1 and S3P2 of every machine cycle and low during all other
states. Thus, the duty cycle of the clock signal is 1:6. Associated with a MOVX instruction the
system clock coincides with the last state (S3) in which a RD or WR signal is active. A timing
diagram of the system clock output is shown in figure 5-12.
Note : During slow-down operation the frequency of the CLKOUT signal is divided by 8.
Semiconductor Group
5-8
1997-08-01