GS2961A Datasheet, PDF (96/104 Pages) Gennum Corporation – Ancillary data extraction

Alternatively, if the test capabilities are to be used in the system, the host processor may
still control the JTAG/HOST input signal, but some means for tri-stating the host must
exist in order to use the interface at ATE. This is represented in Figure 4-43.
Application HOST
GS2961A
CS_TMS
SCLK_TCK
SDIN_TDI
SDOUT_TDO
Tri-State
In-circuit ATE probe
JTAG_HOST
Figure 4-43:System JTAG
Scan coverage is limited to digital pins only. There is no scan coverage for analog pins
VCO, SDO/SDO, RSET, LF, and CP_RES.
The JTAG/HOST pin must be held LOW during scan and therefore has no scan coverage.
Please contact your Semtech representative to obtain the BSDL model for the GS2961A.
4.22 Device Power-up
Because the GS2961A is designed to operate in a multi-voltage environment, any
power-up sequence is allowed. The charge pump, phase detector, core logic, serial
digital output and I/O buffers can all be powered up in any order.
NOTE: Power ramp-up time (10% to 90%) ≥ 40μs.
GS2961A 3Gb/s, HD, SD SDI Integrated Receiver
Data Sheet
54385 - 2
September 2012
96 of 104