GS2961A Datasheet, PDF (40/104 Pages) Gennum Corporation – Ancillary data extraction

20-bit bus
(transition rate = 74.25MHz)
DOUT0[9:0]
Data Stream 1
DOUT1[9:0]
Data Stream 2
10-bit bus
(transition rate = 148.5MHz)
DOUT1[9:0]
PCLK
(148.5MHz)
Figure 4-9:DDR Video Interface - 3G Level B
The GS2961A has the ability to shift the Setup/Hold window on the receive interface, by
using an on-chip delay line to shift the phase of PCLK with respect to the data bus.
The timing of the PCLK output, relative to the data, can be adjusted through the host
interface registers. Address 06Ch contains the delay line controls:
Bit[5] (DEL_LINE_CLK_SEL) is a coarse delay adjustment that selects between the
default (nominal) PCLK phase and a quadrature phase, for a 90º phase shift.
Bits[4:0] (DEL_LINE_OFFSET) comprise a fine delay adjustment to shift the PCLK in
40ps increments (typical conditions). The maximum fine delay adjustment is
approximately 1.2ns under nominal conditions.
An example delay adjustment over min/typ/max conditions is illustrated in Figure 4-10.
The target delay is 0.84 ns under typical conditions (approximately 45º PCLK phase
shift), and requires a control word setting of 0x0014 for address 0x006C.
GS2961A 3Gb/s, HD, SD SDI Integrated Receiver
Data Sheet
54385 - 2
September 2012
40 of 104