GS2961A Datasheet, PDF (77/104 Pages) Gennum Corporation – Ancillary data extraction

conversion, it is recommended to reset the Level B to A converter with the following
sequence:
1. Assert the B to A converter reset by writing '1' to bit 3 of register 05Eh.
2. Monitor H-pulse for a high-to-low transition.
3. De-assert the B to A converter reset by writing '0' to bit 3 of register 05Eh. This must
be completed at the beginning of SAV and should be completed in 1920 PCLK
periods.
4.19 GSPI - HOST Interface
The GSPI, or Gennum Serial Peripheral Interface, is a 4-wire interface provided to allow
the system to access additional status and control information through configuration
registers in the GS2961A.
The GSPI is comprised of a Serial Data Input signal (SDIN), Serial Data Output signal
(SDOUT), an active low Chip Select (CS), and a Burst Clock (SCLK).
Because these pins are shared with the JTAG interface port, an additional control signal
pin JTAG/HOST is provided.
When JTAG/HOST is LOW, the GSPI interface is enabled. When JTAG/HOST is HIGH, the
JTAG interface is enabled.
When operating in GSPI mode, the SCLK, SDIN, and CS signals must be provided by the
system. The SDOUT pin is a non-clocked loop-through of SDIN and may be connected to
the SDIN of another device, allowing multiple devices to be connected to the GSPI chain.
See Section 4.19.2 for details. The interface is illustrated in the Figure 4-36 below.
Application Host
SCLK
CS1
SDOUT
GS2961A
SCLK
CS
SDIN
SDOUT
CS2
SDIN
GS2961A
SCLK
CS
SDIN
SDOUT
Figure 4-36:GSPI Application Interface Connection
All read or write access to the GS2961A is initiated and terminated by the system host
processor. Each access always begins with a Command/Address Word, followed by a
data write to, or data read from, the GS2961A.
GS2961A 3Gb/s, HD, SD SDI Integrated Receiver
Data Sheet
54385 - 2
September 2012
77 of 104