GS2961A Datasheet, PDF (92/104 Pages) Gennum Corporation – Ancillary data extraction

Table 4-18: Configuration and Status Registers (Continued)
Address Register Name Bit Name
023h
FLYWHEEL
_STATUS
RSVD
V_LOCK_DS2
H_LOCK_DS2
RSVD
V_LOCK_DS1
H_LOCK_DS1
024h
RATE_SEL
RSVD
AUTO/MAN
RATE_SEL_TOP
025h
026h
TIM_861_
FORMAT
RSVD
FORMAT_ERR
FORMAT_ID_861
TIM_861_CFG
RSVD
VSYNC_INVERT
HSYNC_INVERT
TRS_861
027h -
036h
RSVD
RSVD
Bit Description
15-5
4
3
2
1
0
15-3
2
1-0
15-7
6
5-0
15-3
2
1
0
−
Reserved.
Indicates that the timing signal
generator is locked to vertical
timing (3G Level B Data Stream 2
only).
Indicates that the timing signal
generator is locked to horizontal
timing (3G Level B Data Stream 2
only).
Reserved.
Indicates that the timing signal
generator is locked to vertical
timing (3G Level B Data Stream 1,
3G Level A, HD and SD inputs).
Indicates that the timing signal
generator is locked to horizontal
timing (3G Level B Data Stream 1,
3G Level A, HD and SD inputs).
Reserved.
Detect data rate automatically (1)
or program manually (0).
Programmable rate select in
manual mode:
0 = HD,
1,3=SD,
2=3G
Reserved.
Indicates standard is not
recognized for CEA 861 conversion.
CEA-861 format ID of input video
stream. Refer to Table 4-9.
Reserved.
Invert output VSYNC pulse.
Invert output HSYNC pulse.
Sets the timing reference outputs
to DFP timing mode when set to
'1'. By default, the timing
reference outputs follow CEA-861
timing mode. Only valid when
TIM_861 is set to '1'.
Reserved.
R/W
R
R
R
R
R
R
R
R/W
R/W
R
R
R
R
R/W
R/W
R/W
R
Default
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
0
0
GS2961A 3Gb/s, HD, SD SDI Integrated Receiver
Data Sheet
54385 - 2
September 2012
92 of 104