GS2961A Datasheet, PDF (70/104 Pages) Gennum Corporation – Ancillary data extraction

4.18 Signal Processing
In addition to error detection and indication, the GS2961A can also correct errors,
inserting corrected code words, checksums and CRC values into the data stream.
The following processing can be performed by the GS2961A:
1. TRS error correction and insertion.
2. HD line based CRC correction and insertion.
3. EDH CRC error correction and insertion.
4. HD line number error correction and insertion.
5. Illegal code re-mapping.
6. Ancillary data checksum error correction and insertion.
7. SMPTE 372M (Level B to Level A) Conversion.
All of the above features are only available in SMPTE mode (SMPTE_BYPASS = HIGH).
To enable these features, the IOPROC_EN/DIS pin must be set HIGH, and the individual
feature must be enabled via bits in the IOPROC_DISABLE register.
The IOPROC_DISABLE register contains one bit for each processing feature allowing
each one to be enabled/disabled individually.
By default (at power up or after system reset), all of the IOPROC_DISABLE register bits
are LOW, enabling all of the processing features.
To disable an individual processing feature, set the corresponding IOPROC_DISABLE bit
HIGH in the IOPROC_DISABLE register.
Table 4-15: IOPROC_DISABLE Register Bits
Processing Feature
TRS error correction and insertion
Y and C line based CRC error correction
Y and C line number error correction
Ancillary data check sum correction
EDH CRC error correction
Illegal code re-mapping
H timing signal configuration
Update EDH Flags
Ancillary Data Extraction
Regeneration of 352M packets
IOPROC_DISABLE Register Bit
TRS_INS
CRC_INS
LNUM_INS
ANC_CHECKSUM_INSERTION
EDH_CRC_INS
ILLEGAL_WORD_REMAP
H_CONFIG
EDH_FLAG_UPDATE_MASK
ANC_DATA_EXT
REGEN_352M
GS2961A 3Gb/s, HD, SD SDI Integrated Receiver
Data Sheet
54385 - 2
September 2012
70 of 104