GS2961A Datasheet, PDF (43/104 Pages) Gennum Corporation – Ancillary data extraction

4.10.2 Automatic Switch Line Lock Handling
The synchronous switch point is defined for all major video standards in SMPTE
RP168-2002. The device automatically re-synchronizes the word alignment block and
timing signal generator at the switch point, based on the detected video standard.
The device, as described in Section 4.10.1 and Figure 4-11 above, implements the
re-synchronization process automatically, every field/frame. The switch line is defined
as follows:
• For 525 line interlaced systems: resynchronization takes place at then end of lines 10 & 273
• For 525 line progressive systems: resynchronization takes place at then end of line 10
• For 625 line interlaced systems: resynchronization takes place at then end of lines 6 & 319
• For 625 line progressive systems: resynchronization takes place at then end of line 6
• For 750 line progressive systems: resynchronization takes place at then end of line 7
• For 1125 line interlaced systems: resynchronization takes place at then end of lines 7 & 568
• For 1125 line progressive systems: resynchronization takes place at then end of line 7
NOTE: Unless indicated by SMPTE 352M payload identifier packets, the GS2961A does
not distinguish between 1125-line progressive segmented-frame (PsF) video and
1125-line interlaced video operating at 25 or 30fps. However. PsF video operating at
24fps is detected by the device.
A full list of all major video standards and switching lines is shown in Table 4-7.
4.10.3 Switch Line Lock Handling During Level B to Level A Conversion
When 3G data is detected by the GS2961A, and Level B to Level A conversion is enabled,
the device only supports a limited phase offset between two synchronous video sources
if a synchronous switch is implemented.
If the synchronous switch point results in an “extended” active video period, the
GS2961A only re-synchronizes to the following TRS ID if the phase difference between
the two sources is less than or equal to 10μs. If the phase difference is greater than 10μs,
the GS2961A takes one additional line to re-synchronize. In this case, the user may
observe a missing H pulse on the line following the switch line, on the H timing output.
Note that this 10μs constraint is only valid when Level B to Level A conversion is
enabled, and only when the synchronous switch point results in an extended active
video area.
GS2961A 3Gb/s, HD, SD SDI Integrated Receiver
Data Sheet
54385 - 2
September 2012
43 of 104