GS2961A Datasheet, PDF (41/104 Pages) Gennum Corporation – Ancillary data extraction

PCLK
PCLK
(MIN)
PCLK
Ranges: _(TYP)
PCLK
(MAX)
90º phase shift
3.367ns
6.734ns
1.684ns
0.842ns
Typical 45º phase shift
3.367ns
6.734ns
1.684ns
Figure 4-10:Delay Adjustment Ranges
4.10 Timing Signal Generator
The GS2961A has an internal timing signal generator which is used to generate digital
FVH timing reference signals, to detect and correct certain error conditions and
automatic video standard detection.
The timing signal generator is only operational in SMPTE mode (SMPTE_BYPASS =
HIGH).
The timing signal generator consists of a number of counters and comparators operating
at video pixel and video line rates. These counters maintain information about the total
line length, active line length, total number of lines per field/frame and total active lines
per field/frame for the received video standard.
It takes one video frame to obtain full synchronization to the received video standard.
NOTE: Both 8-bit and 10-bit TRS words are identified by the device. Once
synchronization has been achieved, the timing signal generator continues to monitor
the received TRS timing information to maintain synchronization.
The timing signal generator re-synchronizes all pixel and line based counters on every
received TRS ID. Note that for correct operation of the timing signal generator, the
SW_EN input pin must be set LOW, unless manual synchronous switching is enabled
(Section 4.10.1).
offset [5] = 1 (90º phase shift)
0.58ns
delay
0.84ns
delay
1.38ns
delay
GS2961A 3Gb/s, HD, SD SDI Integrated Receiver
Data Sheet
54385 - 2
September 2012
41 of 104