GS2961A Datasheet, PDF (38/104 Pages) Gennum Corporation – Ancillary data extraction

SYNCOUT is HIGH whenever a K28.5 sync character is output from the device.
WORDERR is HIGH whenever the device has detected a running disparity error or
illegal code word.
4.9.4 Parallel Output in Data-Through Mode
This mode is enabled when the SMPTE_BYPASS and DVB_ASI pins are LOW.
In this mode, data is passed to the output bus without any decoding, descrambling or
word-alignment.
The output data width (10-bit or 20-bit) is controlled by the setting of the 20bit/10bit pin.
NOTE: In order to use Data-Through Mode, a 3G-B input signal must be connected at the
input of the device when the switch is made from Auto Mode to Data-Through Mode.
4.9.5 Parallel Output Clock (PCLK)
The frequency of the PCLK output signal of the GS2961A is determined by the output
data rate and the 20bit/10bit pin setting. Table 4-6 lists the output signal formats
according to the data format selected in Manual mode (AUTO/MAN bit in the host
interface is set LOW), or detected in Auto Mode (AUTO/MAN bit in the host interface is
set HIGH).
Table 4-6: GS2961A PCLK Output Rates
Output Data
Format
20-bit demultiplexed
HD format
20-bit data output
HD format
20-bit demultiplexed
SD format
20-bit data output
SD format
20-bit demultiplexed
3G format
10-bit multiplexed
3G DDR format
10-bit multiplexed
HD format
10-bit data output
HD format
10-bit multiplexed
SD format
20bit/
10bit
HIGH
HIGH
HIGH
HIGH
HIGH
LOW
LOW
LOW
LOW
Pin/Control Bit Settings
RATE_DET0 RATE_DET1
LOW
LOW
SMPTE_
BYPASS
HIGH
LOW
LOW
LOW
HIGH
X
HIGH
HIGH
X
LOW
LOW
HIGH
HIGH
LOW
HIGH
HIGH
LOW
LOW
HIGH
LOW
LOW
LOW
HIGH
X
HIGH
DVB-ASI
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
PCLK Rate
74.25 or
74.25/1.001MHz
74.25 or
74.25/1.001MHz
13.5MHz
13.5MHz
148.5 or
148.5/1.001MHz
148.5 or
148.5/1.001MHz
148.5 or
148.5/1.001MHz
148.5 or
148.5/1.001MHz
27MHz
GS2961A 3Gb/s, HD, SD SDI Integrated Receiver
Data Sheet
54385 - 2
September 2012
38 of 104