GS2961A Datasheet, PDF (29/104 Pages) Gennum Corporation – Ancillary data extraction

4.4 Serial Digital Loop-Through Output
The GS2961A contains a 100Ω differential serial output buffer which can be configured
to output either a retimed or a buffered version of the serial digital input. The SDO and
SDO outputs of this buffer can interface directly to a 3Gb/s-capable, SMPTE compliant
Gennum cable driver. See 5.3 Typical Application Circuit on page 99.
When the RC_BYP pin is set HIGH, the serial digital output is the re-timed version of the
serial input.
When the RC_BYP pin is set LOW, the serial digital output is simply the buffered version
of the serial input, bypassing the internal reclocker.
The output can be disabled by setting the SDO_EN/DIS pin LOW. The output is also
disabled when the STANDBY pin is asserted HIGH. When the output is disabled, both
SDO and SDO pins are set to VDD and remain static.
The SDO output is muted when the RC_BYP pin is set HIGH and the PLL is unlocked
(LOCKED pin is LOW). When muted, the output is held static at logic ‘0’ or logic ‘1’.
Table 4-1: Serial Digital Output
SDO_EN/DIS
0
1
1
RC_BYP
X
1
0
SDO/SDO
Disabled
Re-timed
Buffered (not re-timed)
NOTE: the serial digital output is muted when the GS2961A is unlocked.
4.5 Serial Digital Reclocker
The GS2961A includes both a PLL stage and a sampling stage.
The PLL is comprised of two distinct loops:
• A coarse frequency acquisition loop sets the centre frequency of the integrated
Voltage Controlled Oscillator (VCO) using an external 27MHz reference clock
• A fine frequency and phase locked loop aligns the VCO’s phase and frequency to
the input serial digital stream
The frequency lock loop results in a very fast lock time.
The sampling stage re-times the serial digital input with the locked VCO clock. This
generates a clean serial digital stream, which may be output on the SDO/SDO output
pins and converted to parallel data for further processing. Parallel data is not affected by
RC_BYP. Only the SDO is affected by this pin.
GS2961A 3Gb/s, HD, SD SDI Integrated Receiver
Data Sheet
54385 - 2
September 2012
29 of 104