GS2961A Datasheet, PDF (55/104 Pages) Gennum Corporation – Ancillary data extraction

2640 Total Horizontal Clocks per line
Data
Enable
720
44
1920 Clocks for Active Video
528
148 clocks
HSYNC
Progressive Frame: 45 Vertical Blanking Lines
1080 Active Vertical Lines
Data
Enable
528
HSYNC
2640 clocks
1121 1122 1123 1124 1125 1 2 3 4 5 6 7
VSYNC
192
41 42
1121 1122 1123 1124 1125
Figure 4-28:H:V:DE Output Timing 1920 x 1080p @ 25 (Format 33)
2200 Total Horizontal Clocks per line
Data
Enable
280
44
88
148 clocks
1920 Clocks for Active Video
HSYNC
Progressive Frame: 45 Vertical Blanking Lines
1080 Active Vertical Lines
Data
Enable
88
HSYNC
2220 clocks
1121 1122 1123 1124 1125 1 2 3 4 5 6 7
VSYNC
192
41 42
1121 1122 1123 1124 1125
Figure 4-29:H:V:DE Output Timing 1920 x 1080p @ 29.97/30 (Format 34)
4.13 Automatic Video Standards Detection
Using the timing extracted from the received TRS signals, the GS2961A is able to identify
the received video standard.
In 3G input mode, the GS2961A measures the timing parameters of one of the two
identical data streams. The Rate Selection/Indication bits and the VD_STD code may be
used in combination to determine the video standard.
The total samples per line, active samples per line, total lines per field/frame and active
lines per field/frame are all measured.
Four registers are provided to allow the system to read the video standard information
from the device. These raster structure registers are provided in addition to the
GS2961A 3Gb/s, HD, SD SDI Integrated Receiver
Data Sheet
54385 - 2
September 2012
55 of 104